Booster circuit

ABSTRACT

A booster circuit is provided which comprises a booster output capacitor and a plurality of capacitors, which are connected in parallel to a booster power supply for being charged when a voltage of a first level is applied to an input terminal of the booster circuit and, on the other hand, connected in series with each other when a voltage of a second level is applied thereto. The alternate application of the voltages having the first and second levels in repetitive manner allows the generation of a boosted voltage across the booster output capacitor.

O United States Patent [191 [111 3,824,447

Kuwabara July 16, 1974 [54] BOOSTER CIRCUIT OTHER PUBLICATIONS 1751lnvemori Tsuneo Kuwabara, Tokyo, Japan H. R. Mallory, Capacitors Add UpIn Voltage Multi- [73] Assignee: Kabushiki Kaisha Daini Seikosha, PElectmmcs, March 2, 19701 P- Tokyo, Japan Sh Primary ExaminerWilliam M.oop, Jr. [22] Filed 1972 Attorney, Agent, or Firm-Eric H. Waters [21]Appl. No.: 310,911

[57] ABSTRACT [30] Foreign Application Priority Data A booster circuitis provided which comprises a Feb. 24, 1972 Japan 47-19237 Dec. 3, 1971Japan 46-97235 [52] US. Cl. 321/15, 307/110 [51] Int. Cl. H02m 7/00 [58]Field of Search 307/109, 110; 321/15 [56] References Cited UNITED STATESPATENTS 3,111,594 1l/l963, Stolte 307/110 3,646,425 2/1972 Beck et a1321/15 booster output'capacitor and a plurality of capacitors, which areconnected in parallel to a booster power supply for being charged when avoltage of a first level is applied to an input terminal of the boostercircuit and, on the other hand, connected in series with each other whena voltage of a second level is applied thereto. The alternateapplication of the voltages having the first andsecond levels inrepetitive manner allowsthe generation of a boosted voltage across thebooster output capacitor.

2 Claims, 10 Drawing Figures Pnzmcnwsm SHEEISIIF4 PATENIED JUL 1 SHEHHIF4 Gum IECCFM mwfi MN mm :5

BOOSTER CIRCUIT FIELD OF INVENTION The present invention relates to abooster circuit, and more particularly to a small-sized booster circuitfor low power with high output voltage and high converting efficiency.

BACKGROUND OF INVENTION Conventionally, well-known booster circuits areequipped with a transformerwhich, however, requires a large space and isnot suitable for use with a power supply source utilized for displaypurposes in small devices such as electronic wrist watches. Moreover, abooster circuit of the voltage doubler type disadvantageously results inlow converting efficiency in its boosting function.

SUMMARY OF INVENTION An object of the present invention is to provide asmall-sized booster circuit with a high output voltage and highconverting efficiency.

Another object of the present invention is to provide a small-sizedbooster circuit capable of being connected to a low-power and highvoltage load such as a liquid crystal panel.

A booster circuit according to the present invention comprises a powersupply; an input terminal to which BRIEF DESCRIPTION OF DRAWING In thedrawing: a

FIG. 1 is an explanatory circuit diagram showing a principle employed ina'booster circuit according to the invention; I

FIG. 2 is another explanatory circuit diagram showing another principleemployed in accordance with the invention; I

FIG. 3 is a schematic circuit diagram of a booster circuit according toone embodiment of the present inventron;

FIGS. 4 and 5 are charts showing the increase of the boosted voltageacross the booster capacitor in response to the variation of the inputsignal; a

FIG. 6 is a schematic circuit diagram of a booster'circuit according toanother embodiment of the present invention;

FIGS. 7 and 8 are, respectively, diagrams of equivalent circuitscorresponding to the circuit of FIG. 6;

FIG. 9 is a chart showing the wave forms produced at the terminals ofthe circuit in FIG. 6; and

FIG. 10 is a chart showing the input and output characteristics of acomplementary MOS FET transistor employed in the present invention.

DETAILED DESCRIPTION FIGS. 1 and 2 are circuit diagrams showingprinciples used in the present invention. In FIG. 1, capacitors C -Chaving the same capacitance are connected in parallel to a booster powersource E having a voltage E. Additionally, a load resistor R and abooster output capacitor C0 are connected in parallel to the powersource E through a switch S As shown in FIG. 1, when the switch S isopened, each capacitor C -C connected in parallel is rapidly charged bythe power source E until the voltage across these capacitors reaches thevoltage E.

In the circuit shown in FIG. 2, the capacitors C -C charged to thevoltage E by the circuit shown in FIG. 1, are connected in series witheach other and with the booster output capacitor C0 and load resistor Rwhen the switch S is closed. In this case, the booster output capacitorC0 is charged to the voltage 4E, that is, the sum of the voltage E ofthe power source E of the booster and the voltages across the threeseries connected capacitor C -C When the load resistor 'R has very highvalue, the voltage /3 C)/(% C C X 4 is applied across thebooster outputcapacitor Co. Assuming that the value of the booster output capacitor C0is less than C the voltage across the booster output capacitor isboosted to a level greater than the voltage E of the booster powersourceE. I

The present invention is realized by application of the above-mentionedtheory or principle,-and com I prisesa switch operating circuit 31 (FIG.3) including a signal generator PCG and inverter IN, electronic 11, 12S13 141 15 S16 S21 2 2 23 d z a. operated by the signals from the switchoperating circuit 31, a booster power source E, capacitors C -C abooster output capacitor C0, and a load resistor R When a signal 0" fromthe signal generator PCG is generated, an output signal I (referred toas a first signal) is produced by the switch operating circuit 31 bymeans of inverter IN and is applied to the gates of MOS field effecttransistors (FET) S S S S S and S (referred to as first F ETs), so as torender the connection'between the drains and sources of the first FETsconductive. j

On the other hand, an output signal 0 from the signal generatorPCG'(note that this is also the first signal from the switch operatingcircuit 31) is applied to the MOS FETs S S S and S (referred to assecond FETs) so as to interrupt the connection between the drains andsource of the second FETs. Accordingly, the circuit in the embodimentshown in FIG. 3 becomes equivalent to the circuit shown in FIG. 1, thuscharging each capacitor C -C rapidly to the same voltage E as thevoltage of the booster power source E.

When the output signal from the generator PCG turns to l (referred to asa second signal), the output of the inverter IN is changed to 0.Accordingly, the first FETs have the connection-between their drains andsources turned off. Therefore, the circuit shown in the embodiment ofFIG. 3 becomes equivalent to the circuit shown in FIG. 2, so that thebooster output capacitor Co is charged by the voltages across thecapacitors charged by the first signal and the voltage of the boosterpower source E. i

The period of the signal generated by the electronic switch operatingcircuit 31 will be next described in connection with FIGS. 4 and 5. Wheneach capacitor C,-C is charged by the booster power source .E as shownin FIG. 1, Le, when the electronic switch 8,, is opened, the dischargingtime constant 1, for the output 4 v pacitor C,, the P-channel MOS FET, Pthe capacitor C the P-channel MOS FET P the capacitor C theswitchingdiode D.,, a booster output capacitor C and capacitor C0 isexpressed by a formula r,=CoR where R, is the resistance of theloadresistor. When the circuit becomes equivalent to the circuit shownin FIG. 2 upon turning off of the switchS a charging time constant 1' isas given by r =[(C/3) Co/(C/3) X Co] X r, where r is the totalconductive resistance of- MOS FETs. Therefore, in order to supply therequired boosted voltage to the load resistor R, in the normal state,the period of the first and second signals from the signal generator PCGshould be shorter than the sum of the charging time constant 1', anddischarging time constant 1',. As shown in FIG. 5, when the first signalgenerating time t, is set to be smaller than the second signalgenerating time 2 so as to make the first signal generating 1, smallerthan the charging time constant 1-,, high boosting efficiency, isrealized.

In FIG. 6, there is shown another embodiment of a booster circuitaccording to the present invention which comprises a booster powersource E for supplying a voltage to a complementary MOS FET M,, andcomplementary MOS FETs M,, M, and M for charging and dischargingcapacitors C,, C, and C Switching diodes D,, D, and D are renderedconductivewhen the capacitors C,, C and C are charged, and renderednon-conductive when the capacitors C,, C and C are discharged and whenbooster output capacitor Co is charged. a 7

When a switch S is connected to a terminal a, the

voltage ofa booster power source E is supplied to inputterminals G,, Gand G, of the complementary MOS field effect transistors M,, M and M torender P- channel MOS FETs P,, P, and P non-conductive and to renderN-channel MOS FETs N,, N and N conductive. As a result, three closedcircuits are formed along the path defined by the positive terminal ofthe booster power source E, the switching diode D, (D D the N-channelMOS FET N, (N N and the negative terminal of the power source,respectively, thus changing the capacitors C,, C, and C to the voltageof the power supply E. Further, the booster output capacitor C ischarged by the booster power source E through the switching diodes D,and D when switch S is connected to the terminal a. Accordingly, thevoltage across the charging capacitance C becomes approximately equal toE, because the diodes D and D, have only a very small resistance. Thecharging state is shown by the equivalent circuit in FIG. 7.

When the switch S is connected to a terminal b, the P-channel channelMOS FET P, in the complementary MOS FET M, is turned on while theN-channel MOS FET N, is turned off, so that the charging capacitor C, isconnected in series with the booster power source E. Simultaneously, theP-channel MOS F ET P of the complementary MOS F ET M is turned on, andthe N- channel MOS FETN is turned off, so that the charging capacitor Cis connected in series through the charging capacitor C, and theP-channel MOS FET P On the other hand, the P-channel MOS FET P, of thecomplementary MOS FET M is turned on, and the N- channel MOS FET isturned off so that the charging capacitor C, is connected through theP-channel MOS FET P At this time. a closed circuit is formed along thepath defined by the positive terminal of the booster power source E, theP-channel MOS FET P,, the cathe negative terminal of the booster powersource E. According to the closed circuit, the booster output capacitorC the booster power source E, the charging capacitor C,, the chargingcapacitor C and the charging capacitor C are connected in series.Consequently, the voltage 4E consisting of the voltages across theseries-connected charging capacitors C,, C and C, and

the power sourceappears across the booster output capacitor through theswitching diode, because the conductive resistance of the P-channel MOSFET is low enought to be negligible. FIG. 8 shows the equivalent circuitof the booster circuit of FIG. 7 in the second state.m

It is to be noted that when the capacitance of the booster outputcapacitor C is larger than that of one of the charging capacitors C,, C,and C the voltage across the capacitor C cannot reach 4E at a time whenthe switch S is alternately turned from a to b.

The-conditions where the switch S is alternately connected to theterminals a and b with repetition willbe described. When the switch S isconnected to the terminal a, the boostercircuit shown in FIG. 6 isrepresented by the equivalent circuit diagram in FIG. 7. Thus the powersupplying terminal V of the complementary MOS FET M, is supplied withthe voltage E from the booster power source. Furthermore, powersupplying terminals V and V of the complementary MOS FETs M and M, aresupplied with the charging voltage for charging the capacitors C, and CA booster output capacitor C is charged by the power supply with a timeconstant defined by the resistance of the switching diodes D and D, andan output capacitor. I

When the switch S is connected 'to the terminalb, the power supplyingterminal V of the complementary MOS FET M, is supplied with the voltageE. The voltage from the booster power source E and across the capacitorC, is applied to the power source terminal V pm of the complementary MOSFET M On the other hand, the voltage 4E, the total of the voltage of thebooster power source E and capacitors C, and C is applied to the powersource terminal V of the complementary MOS FET M Across the boosteroutput capacitor C therefore, appears the voltage which is de-' terminedby the capacitance of the capacitors C,, C, and C and the booster outputcapacitor C The voltage cannot actually reach 4E, even if the forwardvoltage drop of the switching diodes D,, D D and D, were to beneglected. 1

When the switch S is again connected to the terminal a, power supplyingterminals V and V are supplied with the voltage E, while the otherterminal V remains unchanged; The voltage across the booster outputcapacitor is constant so far as the load is not mentary MOS FET whilethe ordinate represents the output voltage therefrom. FIG. 4 shows thatthe higher the power supply voltage to the complementary MOS F ETincreases, the higher the input voltage for switching thecomplementaryMOS FET increases.

As to the switching of the complementary MOS FET M the P-channel FET Pis conductive, and N-channel FET N is non-conductive when the switch Sis connected to the terminal b. However, when the switch S is connectedto the terminal a, the P-channel MOS F ET P becomes non-conductive whilethe N-channel MOS FET N becomes conductive. Accordingly, the voltage ofpower supplying terminal V of the complementary MOS FET M is changed dueto the characteristics m shown in FIG. 4. After the N-channel MOS FET Nof the complementary MOS FET M is conductive, the complementary MOS FETMhd 3 is similarly switched withthe characteristic m shown in FIG.4.'Three capacitors are used in the abovementioned embodiments. It is,however, appreciated that the employment of N capacitors and switchingelements allows the boosted voltage to be N+l times higher than thepower source voltage. .When the MOS FETs are used as electronic switchesas shown in the embodiment of the presentinvention, greater effects areexpected than with usual bipolar transistors. That is, the MOS FETrequires only very little power for controlling because the inputresisof said N type complementary field effect transistors; an inputterminal connected to the gate terminals of said complementary fieldeffect transistors for controlling the output of said each complementaryfield effect transistor element; signal means for applying to said inputterminal a voltage having first and second alternately appearing levels;a plurality of capacitors one terminal of which is connected to thedrain terminal of one of said complementary field effect transistorelements and the other of which is connected to the source terminal ofthe following P type complementary field effect transistor and to thegate terminal thereof and said input terminal through a diode, saidcapacitors being thereby connected in parallel to said power sup ply andcharged when said voltage with the first level is applied to said inputterminal and being connected in series with each other and with saidpower supply when said voltage with the second level is applied to 4said input terminal; and a booster output capacitor tance is very high.Furthermore, the conductive resistance is very low while non-conductiveresistance is very high, so that power dissipation is held to a very lowvalue. Accordingly, converting efficiency for boosting is extremelyhigh. Additionally, the controlling of the gates is advantageouslyrealized only at low voltage, because the gates are connected to ground.

As mentioned above, the present invention comprises complementary MOSFETs for switching the connection of the capacitors from parallelconnection to series connection relative to the booster power source, sothat switching requires only very little power.

Furthermore, the present invention is suitable for use as a small-sizedbooster circuit because of the use of integrated MOS FETs, diodes andcapacitors. Accordingly, the booster circuit according to the presentinvention is adapted for use as a booster circuit for a watch wherein aliquid crystal display panel is employed because the liquid crystal hasextremely high resistance.

What is claimed is:

1. A booster circuit comprising a plurality of complementary fieldeffect transistor elements each including P type and N typecomplementary field effect transistors having source, drain and gateterminals in drain-todrain and gate-to-gate configuration; a boosterpower supply for supplying a voltage to the source terminals connectedin series with said plurality of capacitors and said power supply whensaid voltage of the second level is applied to said input terminal,thereby producing a boosted voltage across said booster outputcapacitor.

2. A booster circuit comprising a plurality of field effect transistorelements each including two field effect transistors of one polarityhaving source, drain and gate terminals, a capacitor connected betweenthe source terminal of one of said two field effect transistors and thedrain terminal of the other thereof; a booster power supply forsupplying a voltage to the drain terminals of said one of two fieldeffect-transistors in said field effect transistor elements; an inputterminal connected to the gate terminals of said field effecttransistors for controlling the output of said field effect transistorelement; a second plurality of field effect transistors having source,drain, and gate terminals, the source and drain terminals thereof beingconnected in series with said plurality of capacitors and said boosterpower supply, and the gate terminals thereof being connected to saidinput terminal; signal means for applying to said input terminal avoltage having first and second alternately appearing levels, saidcapacitors being thereby connected in parallel to said power supply andcharged when said voltage with the first level is applied to the gateterminals of said field effect transistor element and being connected inseries with each other and with said power supply when said voltage withthe second level is applied to said gate terminals of said secondplurality of field effect transistors; and a booster output capacitorconnected in series with said plurality of capacitors and said powersupply when said voltage of the second level is applied to said gateterminal of said second plurality of field effect, thereby producing aboosted voltage across said booster output capacitor.

1. A booster circuit comprising a plurality of complementary fieldeffect transistor elements each including P type and N typecomplementary field effect transistors having source, drain and gateterminals in drain-to-drain and gate-to-gate configuration; a boosterpower supply for supplying a voltage to the source terminals of said Ntype complementary field effect transistors; an input terminal connectedto the gate terminals of said complementary field effect transistors forcontrolling the output of said each complementary field effecttransistor element; signal means for applying to said input terminal avoltage having first and second alternately appearing levels; aplurality of capacitors one terminal of which is connected to the drainterminal of one of said complementary field effect transistor elementsand the other of which is connected to the source terminal of thefollowing P type complementary field effect transistor and to the gateterminal thereof and said input terminal through a diode, saidcapacitors being thereby connected in parallel to said power supply andcharged when said voltage with the first level is applied to said inputterminal and being connected in series with each other and with saidpower supply when said voltage with the second level is applied to saidinput terminal; and a booster output capacitor connected in series withsaid plurality of capacitors and said power supply when said voltage oftHe second level is applied to said input terminal, thereby producing aboosted voltage across said booster output capacitor.
 2. A boostercircuit comprising a plurality of field effect transistor elements eachincluding two field effect transistors of one polarity having source,drain and gate terminals, a capacitor connected between the sourceterminal of one of said two field effect transistors and the drainterminal of the other thereof; a booster power supply for supplying avoltage to the drain terminals of said one of two field effecttransistors in said field effect transistor elements; an input terminalconnected to the gate terminals of said field effect transistors forcontrolling the output of said field effect transistor element; a secondplurality of field effect transistors having source, drain, and gateterminals, the source and drain terminals thereof being connected inseries with said plurality of capacitors and said booster power supply,and the gate terminals thereof being connected to said input terminal;signal means for applying to said input terminal a voltage having firstand second alternately appearing levels, said capacitors being therebyconnected in parallel to said power supply and charged when said voltagewith the first level is applied to the gate terminals of said fieldeffect transistor element and being connected in series with each otherand with said power supply when said voltage with the second level isapplied to said gate terminals of said second plurality of field effecttransistors; and a booster output capacitor connected in series withsaid plurality of capacitors and said power supply when said voltage ofthe second level is applied to said gate terminal of said secondplurality of field effect, thereby producing a boosted voltage acrosssaid booster output capacitor.